Automated test equipment (ATE) can be any testing assembly that performs a test on a device, semiconductor wafer or die, etc. ATE assemblies may be used to execute automated tests that quickly perform measurements and generate test results that can then be analyzed. An ATE assembly may be anything from a computer system coupled to a meter, to a complicated automated test assembly that may include a custom, dedicated computer control system and many different test instruments that are capable of automatically testing electronics parts and/or semiconductor. Automatic Test Equipment (ATE) is commonly used within the field of electrical chip manufacturing. ATE systems both reduce the amount of time spent on testing devices to ensure that the device functions as designed and serve as a diagnostic tool to determine the presence of faulty components within a given device before it reaches the consumer.
In testing devices or products, e.g. after production, it is crucial to achieve among others a high product quality, an estimation of the device or product performance, a feedback concerning the manufacturing process and finally a high customer contentment. Usually a plurality of tests is performed in order to ensure the correct function of a device or product, commonly referred to as a device under test (“DUT”) in testing parlance. The plurality of tests is typically part of a test plan that is loaded into the ATE system by the user. The test plan acts as a blueprint for running the tests on the DUTs. The plurality of tests may be compiled in a test flow wherein the test flow may be separated into different test groups which contain one or more tests for testing the device or product. For example, a semiconductor device may be tested with a test flow comprising contact tests, current-voltage tests, logic tests, speed tests, stress tests and functional tests.
Testing memory type DUTs, e.g., NAND flash packages requires some type of error capture and analysis. Conventional ATE solutions for testing memory type DUTs typically capture an entire bitmap of the memory array for the DUT where the errors can be seen can be observed within a 2-dimensional representation of the memory array in the x-y plane and analyzed. This can be particularly onerous from a resource perspective as memory arrays in current and future memory devices continue to grow. For example, current typical NAND devices can typically store anywhere from 32 Gigabits (Gb) to 128 Gb of information. Further, a typical ATE system can test hundreds of DUTs in parallel. Accordingly, being able to store entire bitmaps for all the DUTs can become exceedingly expensive, both from a memory storage and processing perspective, if not impossible due to tester hardware physical limitations. Not only does storing all the bitmaps require a considerable amount of memory, but also high performance processors are required to rapidly scan all the stored information and find all the fail related information in as short a duration as possible. Further, the larger memory sizes required in typical ATE solutions is an impediment to increase tester parallelism because of the high cost required to build the tester.
Further, another limitation with conventional ATE solution for testing memory type DUTs is that all the failure analyses on the DUTs are conducted during post-processing steps after the entire bitmap arrays have been captured for the respective devices using external error capture memory. It is only after capturing the full bit-maps of the failed memory arrays that the ATE controller of a conventional tester can analyze them to determine how to get rid of bad bits in the memory array and the most efficient way to repair the device if possible. Waiting for all the information to be collected from the DUTs before beginning the redundancy and failure analyses introduces unnecessary latency in the testing process and adds to the cost.